Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-37
used by the receiver. The received data bits are transferred into the internal shift register after the data
strobing. If noise or framing errors are detected, this is flagged as described in Section 31.4.5.4, Reception
Error Reporting.
31.4.5.3.14 Bit Synchronization
To adjust for baud rate mismatch, a synchronization of the cyclic sample counter RSC is performed during
start bit reception as described in Section 31.4.5.3.15, Start Bit Sampling.
Additionally, the synchronization of the cyclic sample counter RSC can be configured to be performed
during data bit reception as described in Section 31.4.5.3.16, Data Bit Sampling.
31.4.5.3.15 Start Bit Sampling
Figure 31-32. Start Bit Sampling and Strobing
Start Bit Qualification
To adjust for baud rate mismatch, the cyclic sample counter RSC is re-synchronized by reset after
successful start bit qualification. A start bit is successfully qualified, if no reception is ongoing and three
consecutive high samples are followed immediately by a low sample.
Start Bit Verification
After the successful start bit qualification the receiver starts to verify the start bit by a two out of three
samples majority voting.
A start bit is verified if at least two out of the three sample RSC3, RSC5, and RSC5 are sampled low. Noise
is detected when exactly one out of the three samples is high. The results of the start bit verification is
summarized in Table 31-29.
Table 31-29. Start Bit Verification Result
[RS3, RS5, RS7] Start Bit Verified Noise Detected
000 Yes No
001 Yes Yes
010 Yes Yes
1
Sampled Value
RCLK
START BIT
Receiver Input
START BIT
QUALIFICATION
11111000 0000
4 5 6 7 8 2
sample counter reset
3
RSC
4 5 6 7
0
8 9 10 11 12 13 14 15 16 1
00
START BIT
VERIFICATION
NOISE
DETECTION
data strobing
01001000
2
sample counter wrap
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