Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-39
31.4.5.3.17 Data Bit Synchronization
To adjust for baud rate mismatch during the reception of data bits, the cyclic sample counter RSC can be
configured to be synchronized on falling edges during data bit reception. This kind of synchronization is
performed only if the synchronization mode bit SYNM in the eSCI Control Register 3 (eSCI_CR3) is 0.
Data Bit Synchronization (Right Shifted Edges)
This kind of sample counter synchronization happens if the transmitter is slower than the receiver. The
reset behavior of the sample counter is shown in Figure 31-34. The sample counter reset condition is:
1. The data bit N-1 is sampled as 1, and
2. the data bit N is sampled as 0, and
3. a falling edge consisting of three consecutive 1-samples and a following 0-sample is detected, and
4. the 0-sample of the falling edge is received at data bit N sample j, with 1 <= j <= 8.
If the condition is fulfilled, the sample counter is reset 16 RCLK cycles after the 0 of the falling edge
condition was received. The bit counter is not increased.
Figure 31-34. Data Bit Synchronization (Right Shifted Edges)
Table 31-31. Data Bit Sampling
[RS8, RS9, RS10] Data Bit Value Noise Detected
000 0 No
001 0 Yes
010 0 Yes
100 0 Yes
011 1 Yes
101 1 Yes
110 1 Yes
111 1 No
VOTING
DATA
RCLK
RXD
2 3
RSC
4 5 6 7 8 9 10 11 12 13 1415 16 1 2
wrap
1
wrap
3
sample counter reset
right shifted falling edge
FALLING
EDGE
2 3 4 5 6 7 8 9 10 1112 13 14 15161 2 3 4 5 6 7 8 9 10 11 12 13 1415 161
VOTING
DATA
reset
VOTING
DATA
DATA BIT N – 1 DATA BIT N DATA BIT N + 1
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