NXP Semiconductors PXN2020 - Page 1171

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-21
Figure 36-11. NEXUS Controller State Machine
Selecting a Nexus Client Register
When the NEXUS-ENABLE instruction is decoded by the TAP controller, the input port allows
development tool access to all Nexus registers. Each register has a 7-bit address index.
All register access is performed via the SELECT-DR-SCAN path of the IEEE 1149.1–2001 TAP
controller state machine. The Nexus controller defaults to the REG_SELECT state when enabled.
Accessing a register requires two passes through the SELECT-DR-SCAN path: one pass to select the
register and the second pass to read/write the register.
The first pass through the SELECT-DR-SCAN path is used to enter an 8-bit Nexus command consisting
of a read/write control bit in the LSB followed by a 7-bit register address index, as illustrated in
Figure 36-12. The read/write control bit is set to 1 for writes and 0 for reads.
Table 36-11. Loading NEXUS-ENABLE Instruction
Clock TDI TMS IEEE 1149.1 State Nexus State Description
0 — 0 RUN-TEST/IDLE IDLE IEEE 1149.1-2001 TAP controller in idle state
1 — 1 SELECT-DR-SCAN IDLE Transitional state
2 — 1 SELECT-IR-SCAN IDLE Transitional state
3 — 0 CAPTURE-IR IDLE Internal shifter loaded with current instruction
4 — 0 SHIFT-IR IDLE TDO becomes active, and the IEEE 1149.1-2001
shifter is ready. Shift in all but the last bit of the
NEXUS_ENABLE instruction.
5-7 0 0 3 TCKS in SHIFT-IR IDLE
8 0 1 EXIT1-IR IDLE Last bit of instruction shifted in
9 — 1 UPDATE-IR IDLE NEXUS-ENABLE loaded into instruction register
10 — 0 RUN-TEST/IDLE REG_SELECT Ready to be read/write Nexus registers
Figure 36-12. IEEE 1149.1 Controller Command Input
MSB LSB
7-bit register index R/W
IDLE
NEXUS-ENABLE = 1
REG_SELECT
UPDATE-DR = 1
DATA_ACCESS
UPDATE-DR = 1
NEXUS-ENABLE = 1 &&
NEXUS-ENABLE = 0
TEST-LOGIC-RESET = 1
UPDATE-IR = 1