Memory Map
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor A-109
0x0868
SIU_GPDI104_107—GPIO pin data input register 104 – 107
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x086C
SIU_GPDI108_111—GPIO pin data input register 108 – 111
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0870
SIU_GPDI112_115—GPIO pin data input register 112 – 115
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0874
SIU_GPDI116_119—GPIO pin data input register 116 – 119
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0878
SIU_GPDI120_123—GPIO pin data input register 120 – 123
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x087C
SIU_GPDI124_127—GPIO pin data input register 124 – 127
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0880
SIU_GPDI128_131—GPIO pin data input register 128 – 131
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0884
SIU_GPDI132_135—GPIO pin data input register 132 – 135
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0888
SIU_GPDI136_139—GPIO pin data input register 136 – 139
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x088C
SIU_GPDI140_143—GPIO pin data input register 140 – 143
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0890
SIU_GPDI144_147—GPIO pin data input register 144 – 147
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0894
SIU_GPDI148_151—GPIO pin data input register 148 – 151
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x0898
SIU_GPDI152_154—GPIO pin data input register 152 – 154
R/W
0x0U0U_0U0U
8.3.2.15/8-28
0x089C–0x0903 Reserved
0x0904 SIU_ISEL1—IMUX select register 1 R/W 0x0000_0000 8.3.2.16/8-29
0x0908 SIU_ISEL2—IMUX select register 2 R/W 0x0000_0000 8.3.2.17/8-33
0x090C–0x090F Reserved
0x0910 SIU_ISEL4—IMUX select register 4 R/W 0x0000_0000 8.3.2.18/8-35
0x0914–0x097F Reserved
0x0980 SIU_CCR—Chip configuration register R/W 0x000U_0000 8.3.2.19/8-36
0x0984 SIU_ECCR—External clock control register R/W 0x0000_1001 8.3.2.20/8-37
0x0988 SIU_GPR0—General purpose register 0 R/W 0x0000_0000 8.3.2.21/8-38
0x098C SIU_GPR1—General purpose register 1 R/W 0x0000_0000 8.3.2.21/8-38
0x0990 SIU_GPR2—General purpose register 2 R/W 0x0000_0000 8.3.2.21/8-38
0x0994 SIU_GPR3—General purpose register 3 R/W 0x0000_0000 8.3.2.21/8-38
0x0998–0x099B Reserved
0x09A0 SIU_SYSCLK—System clock register R/W 0x0000_0000 8.3.2.22/8-38
0x09A4 SIU_HLT0—Halt request 0 R/W 0x0000_0000 8.3.2.23/8-39
0x09A8 SIU_HLT1—Halt request 1 R/W 0x0000_0000 8.3.2.23/8-39
0x09AC SIU_HLTACK0—Halt acknowledge 0 R/W 0x0000_0000 8.3.2.24/8-41
0x09B0 SIU_HLTACK1—Halt acknowledge 1 R/W 0x0000_0000 8.3.2.24/8-41
0x09B4 SIU_EMIOS_SEL0—eMIOS select register 0 R/W 0x0000_0000 8.3.2.25/8-44
Table A-4. PXN20 Detailed Register Map (continued)
Address Offset
from Module Base
Register
Access
1
Reset Value
2
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