NXP Semiconductors PXN2020 - Page 1369

Memory Map
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor A-111
0x0D14 SIU_DSPICL—Masked serial GPO register for DSPI_C Low R/W 0x0000_0000 8.3.2.51/8-60
0x0D18 SIU_DSPIDH—Masked serial GPO register for DSPI_D High R/W 0x0000_0000 8.3.2.52/8-61
0x0D1C SIU_DSPIDL—Masked serial GPO register for DSPI_D Low R/W 0x0000_0000 8.3.2.53/8-62
0x0D20–0x0D43 Reserved
0x0D44 SIU_EMIOSA—eMIOS select register for DSPI_A R/W 0x0000_0000 8.3.2.54/8-62
0x0D48 SIU_DSPIAHLA—SIU_DSPIAH/L select register for DSPI_A R/W 0x0000_0000 8.3.2.55/8-63
0x0D4C–0x0D53 Reserved
0x0D54 SIU_EMIOSB—eMIOS select register for DSPI_B R/W 0x0000_0000 8.3.2.56/8-64
0x0D58 SIU_DSPIBHLB—SIU_DSPIBH/L select register for DSPI_B R/W 0x0000_0000 8.3.2.57/8-64
0x0D5C–0x0D63 Reserved
0x0D64 SIU_EMIOSC—eMIOS select register for DSPI_C R/W 0x0000_0000 8.3.2.58/8-65
0x0D68 SIU_DSPICHLC—H/L select register for DSPI_C R/W 0x0000_0000 8.3.2.59/8-65
0x0D6C–0x0D73 Reserved
0x0D74 SIU_EMIOSD—eMIOS select register for DSPI_D R/W 0x0000_0000 8.3.2.60/8-66
0x0D78–0x0D7B SIU_DSPIDHLD—SIU_DSPIDH/L select register for DSPI_D R/W 0x0000_0000 8.3.2.61/8-67
0x0D7C–0x3FFF Reserved
0xFFFE_C000
CRP
Chapter 6, Clocks, Reset, and Power (CRP)
0x0000 CRP_CLKSRC—Clock source register R/W 0x0001_1F3F 6.2.2.1/6-5
0x0004–0x000F Reserved
0x0010 CRP_RTCC—RTC control register R/W 0x0000_0000 6.2.2.2/6-6
0x0014 CRP_RTSC—RTC status register R 0x0000_0000 6.2.2.3/6-8
0x0018 CRP_RTCCNT—RTC counter register R 0x0000_0000 6.2.2.4/6-9
0x001C–0x003F Reserved
0x0040 CRP_PWKENH—Pin wakeup enable high register R/W 0x0000_0000 6.2.2.5/6-9
0x0044 CRP_PWKENL—Pin Wakeup enable low register R/W 0x0000_0000 6.2.2.5/6-9
0x0048 CRP_PWKSRCIE—Pin wakeup source interrupt enable
register
R/W 0x0000_0000 6.2.2.6/6-11
0x004C CRP_PWKSRCF—Pin wakeup source flag register R 0x0000_0000 6.2.2.7/6-11
0x0050 CRP_Z6VEC—Z6 reset vector register R/W 0xFFFF_0001 6.2.2.8/6-12
0x0054 CRP_Z0VEC—Z0 reset vector register R/W 0xFFFF_FFFE 6.2.2.9/6-12
0x0058 CRP_RECPTR—Recovery pointer register R/W
0xFFFF_FFFC 6.2.2.10/6-13
0x005C–0x005F Reserved
Table A-4. PXN20 Detailed Register Map (continued)
Address Offset
from Module Base
Register
Access
1
Reset Value
2
Section/Page