NXP Semiconductors PXN2020 - Page 1370

Memory Map
PXN20 Microcontroller Reference Manual, Rev. 1
A-112 Freescale Semiconductor
0x0060 CRP_PSCR—Power status and control register R/W 0x0000_0000 6.2.2.11/6-14
0x0064–0x006F Reserved
0x0070 CRP_SOCSC—SoC status and control register R/W 0x4000_0020 6.2.2.12/6-15
0x0074–0x03FF Reserved
0xFFFF_0000
PLL
Chapter 7, Frequency Modulated Phase-Locked Loop (FMPLL)
0x0000 Reserved
0x0004 SYNSR—FMPLL synthesizer status register R/W —
6
7.3.2.1/7-3
0x0008 ESYNCR1—FMPLL enhanced synthesizer control register 1 R/W 0x8000_0030 7.3.2.2/7-5
0x000C ESYNCR2—FMPLL enhanced synthesizer control register 2 R/W 0x0000_0003 7.3.2.3/7-7
0x0010–0x3FFF Reserved
0xFFFF_4000 –
0xFFFF_7FFF
Reserved
0xFFFF_8000
PFlash Configuration
Chapter 12, Flash Memory Array and Control
0x0000 MCR—Module configuration register R/W 0x0540_0600
12.3.2.1/12-6
0x0004 LML—Low-/Mid-address space block locking register R/W 0x0013_03FF 12.3.2.2/12-10
0x0008 HBL—High-address space block locking register R/W 0x0000_003F 12.3.2.3/12-12
0x000C SLL—Secondary low-/mid-address space block locking
register
R/W 0x0013_03FF 12.3.2.4/12-13
0x0010 LMS—Low-/mid-address space block select register R/W 0x0000_0000 12.3.2.5/12-14
0x0014 HBS—High-address space block select register R/W 0x0000_0000 12.3.2.6/12-15
0x0018 ADR—Address register R/W 0x0000_0000 12.3.2.7/12-16
0x001C PFCRP0—Platform flash configuration register for port 0 R/W 0x0800_FF00 12.3.2.8/12-17
0x0020 PFCRP1—Platform flash configuration register for port 1 R/W 0x3000_FF00 12.3.2.8/12-17
0x0024 PFAPR—Platform flash access protection register R/W 0x00FF_FE00 12.3.2.9/12-20
0x0028 PFSACC—Platform flash supervisor access control register R/W 0x00FF_FE08 12.3.2.10/12-21
0x002C PFDACC—Platform flash data access control register R/W 0x00FF_FE10 12.3.2.11/12-23
0x0030 – 0x0038 Reserved
0x003C UT0—UTest register 0 R/W 0x0000_0001 12.3.2.12/12-23
0x0040 UT0—UTest register 1 R/W 0x0000_0000 12.3.2.13/12-25
0x0044 UT0—UTest register 2 R/W 0x0000_0000 12.3.2.14/12-26
0x0048 UM0—User multiple input signature register 0 R/W 0x0000_0000 12.3.2.15/12-26
Table A-4. PXN20 Detailed Register Map (continued)
Address Offset
from Module Base
Register
Access
1
Reset Value
2
Section/Page