e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-19
13.3.1.5.3 MAS[2] Register
The MAS[2] register is shown in Figure 13-9.
MAS[2] fields are defined in Table 13-6.
TS Translation address space.
This bit is compared with the IS or DS fields of the MSR (depending on the type of access) to determine if this TLB
entry can be used for translation.
TSIZE Entry page size.
Supported page sizes are:
0001 4 KB 0110 4 MB
0010 16 KB 0111 16 MB
0011 64 KB 1000 64 MB
0100 256 KB 1001 256 MB
0101 1 MB
All other values are undefined.
SPR: 626 Access: Read/write
012345678910111213141516171819202122232425262728293031
R
EPN —
VL
E
WIMGE
W
Reset Undefined on Power Up Unchanged on Reset
Figure 13-9. MMU Assist Register 2—MAS[2]
Table 13-6. MAS[2]—EPN and Page Attributes
Field Description
EPN Effective page number [0:19].
VLE Power Architecture VLE.
0 This page is a standard Book E page.
1 This page is a Power Architecture VLE page.
W Write-through required.
0 This page is considered write-back with respect to the caches in the system.
1 All stores performed to this page are written through to main memory.
I Cache inhibited.
0 This page is considered cacheable.
1 This page is considered cache-inhibited.
M Memory coherence required.The e200z6 does not
support the memory coherence required attribute, and thus it is
ignored.
0 Memory coherence is not required.
1 Memory coherence is required.
Table 13-5. MAS[1]—Descriptor Context and Configuration Control (continued)
Field Description
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