NXP Semiconductors PXN2020 - Page 544

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-24 Freescale Semiconductor
Figure 24-18 and Table 24-20 define the fields of the TCDn structure.
NOTE
The TCD structures for the eDMA channels shown in Figure 24-18 are
implemented in internal SRAM. These structures are not initialized at reset;
therefore, all channel TCD parameters must be initialized by the application
code before activating that channel.
0x1000+(32 x n)+0x000C Last source address adjustment (slast)
0x1000+(32 x n)+0x0010 Destination address (daddr)
0x1000+(32 x n)+0x0014 Current major iteration count (citer) Signed destination address offset (doff)
0x1000 (32 x n) 0x0018 Last destination address adjustment / scatter-gather address (dlast_sga)
0x1000+(32 x n)+0x001c Beginning major iteration count (biter) Channel control/status
Word
Offset
012345678910111213141516171819202122232425262728293031
0x0000 SADDR
0x0004 SMOD SSIZE DMOD DSIZE SOFF
0x0008 NBYTES
1
1
The fields implemented in Word 2 depend on whether EDMA_CR(EMLM) is set to 0 or 1. Refer to Table 24-3.
0x8
SMLOE
1
DMLOE
1
MLOFF or NBYTES
1
NBYTES
1
0x000C SLAST
0x0010 DADDR
0x0014
CITER.E_ LINK
CITER or
CITER.LINKCH
CITER DOFF
0x0018 DLAST_SGA
0x001C
BITER.E_ LINK
BITER or
BITER.LINKCH
BITER BWC MAJOR LINKCH
DONE
ACTIVE
MAJOR.E_LINK
E_SG
D_REQ
INT_HALF
INT_MAJ
START
012345678910111213141516171819202122232425262728293031
Figure 24-18. TCD Structure
Table 24-19. TCDn 32-bit Memory Structure (continued)
eDMA Offset TCDn Field