Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-32 Freescale Semiconductor
Figure 24-19. eDMA Operation, Part 1
In the second part of the basic data flow as shown in Figure 24-20, the modules associated with the data
transfer (address path, data path, and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data path module until it is gated onto the system bus during the destination write.
This source read/destination write processing continues until the inner minor byte count has been
transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer.
Slave interface
eDMA
eDMA peripheral request
System bus
Data path
Control
Address
Program model/
Slave write data
Slave write address
Bus write data
Slave read data
Bus address
eDMA engine
TCD0
TCDn-1*
eDMA interrupt request
Bus read data
channel arbitration
eDMA done handshake
path
SRAM
Transfer control descriptor
(TCD)
SRAM
*n = 32 channels
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