Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-33
Figure 24-20. eDMA Operation, Part 2
After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the address path logic performs the required updates to certain fields in the channel’s TCD;
for example, SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then there are
additional operations performed. These include the final address adjustments and reloading of the BITER
field into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a
possible fetch of a new TCD from memory using the scatter-gather address pointer included in the
descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in
Figure 24-21.
Slave interface
eDMA
eDMA interrupt request
System bus
Program model/
Slave write data
Slave write address
Bus write data
Slave read data
Bus address
eDMA engine
TCD0
TCDn-1*
eDMA peripheral
Bus read data
channel arbitration
request
SRAM
Transfer control descriptor
(TCD)
SRAM
Data path
Control
Address
path
eDMA done handshake
*n = 32 channels
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