NXP Semiconductors PXN2020 - Page 778

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
27-6 Freescale Semiconductor
0x0048 CCBCR0—Channel 0 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x004C CNBCR0—Channel 0 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x0050 CECR1—Channel 1 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
0x0054 CSCR1—Channel 1 Status Configuration Register R/W 0x8000_0000 27.3.2.12/27-19
0x0058 CCBCR1—Channel 1 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x005C CNBCR1—Channel 1 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x0060 CECR2—Channel 2 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
0x0064 CSCR2—Channel 2 Status Configuration Register R/W 0x8000_0000 27.3.2.12/27-19
0x0068 CCBCR2—Channel 2 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x006C CNBCR2—Channel 2 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x0070 CECR3—Channel 3 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
0x0074 CSCR3—Channel 3 Status Configuration Register R/W 0x8000_0000 27.3.2.12/27-19
0x0078 CCBCR3—Channel 3 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x007C CNBCR3—Channel 3 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x0080 CECR4—Channel 4 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
0x0084 CSCR4—Channel 4 Status Configuration Register R/W 0x8000_0000 27.3.2.12/27-19
0x0088 CCBCR4—Channel 4 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x008C CNBCR4—Channel 4 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x0090 CECR5—Channel 5 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
0x0094 CSCR5—Channel 5 Status Configuration Register R/W 0x8000_0000 27.3.2.12/27-19
0x0098 CCBCR5—Channel 5 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x009C CNBCR5—Channel 5 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x00A0 CECR6—Channel 6 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
0x00A4 CSCR6—Channel 6 Status Configuration Register R/W 0x8000_0000 27.3.2.12/27-19
0x00A8 CCBCR6—Channel 6 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x00AC CNBCR6—Channel 6 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x00B0 CECR7—Channel 7 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
0x00B4 CSCR7—Channel 7 Status Configuration Register R/W 0x8000_0000 27.3.2.12/27-19
0x00B8 CCBCR7—Channel 7 Current Buffer Configuration Register R/W 0x0000_0000 27.3.2.13/27-22
0x00BC CNBCR7—Channel 7 Next Buffer Configuration Register R/W 0x0000_0000 27.3.2.14/27-23
0x00C0 CECR8—Channel 8 Entry Configuration Register R/W 0x0000_0000 27.3.2.11/27-17
Table 27-7. MLB Memory Map (continued)
Offset from
MLB_BASE
(
0xC3F8_4000)
Register Access Reset Value Section/Page