EasyManua.ls Logo

NXP Semiconductors PXN2020 - Page 855

NXP Semiconductors PXN2020
1376 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-33
Triggering of the internal counter is done by a rising or falling edge or both edges on the input signal. The
polarity and the triggering edge is selected by EDSEL and EDPOL bits in EMIOS_CCR[n] register.
Register A1 holds the start time and register B1 holds the stop time for the time window. After writing to
register A1, when a match occur between comparator A and the selected timebase, the internal counter is
cleared and it is ready to start counting input events. When the time base matches comparator B, the
internal counter is disabled and its content is transferred to register A2. At the same time the FLAG bit is
set. Reading registers EMIOS_CCNTR[n] or A2 returns the amount of detected pulses.
For continuous operation (MODE[6] cleared, MODE[0:6] = 000_1010), the next match between
comparator A and the selected time base clears the internal counter and counting is enabled again. In order
to guarantee coherent measurements when reading EMIOS_CCNTR[n] after the FLAG is set, the software
must check if the time base value is out of the time interval defined by registers A1 and B1. Alternatively
register A2 always holds the latest available measurement providing coherent data at any time after the
first FLAG had occurred. This register is addressed by the alternate address EMIOS_ALTA[n].
For single shot operation (MODE[6] set, MODE[0:6] = 000_1011), the next match between comparator
A and the selected time base has no effect, until a new write to register A is performed. The
EMIOS_CCNTR content is also transferred to register A2 when a match in the B comparator occurs.
Figure 28-29 and Figure 28-30 show how the Unified Channel can be used for continuous or single shot
pulse/edge counting mode.
Figure 28-29. Pulse/Edge Counting Continuous Mode Example
amount of events detected
0x000000
EMIOS_CCNTR[n]
Time
B1 Match
Flag Pin/Register
A1 B1 write
Selected Counter Bus
0x0003030x000090
0x0003030x000090
A1 Value
1
0x0000900x000090
B1 Match A1 Match
amount of events detected
B1 Value
2
0x000303 0x000303 0x000303
A1 Match
0x000090
Notes: 1. EMIOS_CADR[n] = A1
2. EMIOS_CBDR[n] = B1
MODE = 000_1010
3. EMIOS_ALTA[n] = A2
A2 Value
3
A2 EMIOS_CCNTR[n]
A2
EMIOS_CCNTR[n]

Table of Contents

Related product manuals