Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-39
Figure 28-36. Modulus Counter Buffered (MCB) Up/Down Mode
Figure 28-37 shows the A1 register update process in up counter mode. The A1 load signal is generated
based on the detection of the internal counter reaching one and has the duration of one system clock cycle.
During the load pulse, A1 still holds its previous value. It is updated at the second system clock cycle only.
Figure 28-37. MCB Mode A1 Register Update in Up Counter Mode
Figure 28-38 shows the A1 register update in up/down counter mode. Note that A2 can be written at any
time within cycle (n) in order to be used in cycle (n + 1). Thus A1 receives this new value at the next cycle
boundary. The update disable bits (OU[n] in EMIOS_OUDR) can be used to disable the update of A1
register.
EMIOS_CCNTR[n]
Time
Write to A2
A1 Match
A1 Match
Write to A2
0x000001
0x000005
0x000006
0x000007
FLAG Set Event
0x000005 0x000007
A2 Value
A1 Value
0x000006
0x000005
0x000007
A1 Value 0x000008
0x000008
0x000001
Internal Counter
0x000004
0x000006
A2 Value 0x000008 0x000004 0x000006
0x000002
0x000004 0x000006
Write to A2
A1 Load Signal
8
4
6
Counter = A1
Time
Cycle n
Cycle n +1
Cycle n +2
A1 Match A1 MatchA1 Match
Write to A2
1
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