Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-46 Freescale Semiconductor
Figure 28-44. OPWMCB A1 and B1 Registers Load
The (OU[n] in EMIOS_OUDR) bit can be used to disable the A1 and B1 updates, thus allowing to
synchronize the load on these registers with the load of A1 or B1 registers in others channels. Using the
update disable bit, A1 and B1 registers can be updated at the same counter cycle, allowing both registers
to change at the same time.
In this mode A1 matches always sets the internal counter to 0x00_0001. When operating with leading edge
dead time insertion the first A1 match sets the internal counter to 0x00_0001. When a match occurs
between register B1 and the internal time base, the output flip-flop is set to the value of the EDPOL bit. In
the following match between register A1 and the selected time base, the output flip-flop is set to the
complement of the EDPOL bit. This sequence repeats continuously. The internal counter should not reach
0x00_0000 as consequence of a rollover. To avoid this, the user must not write a value greater than twice
the difference between external count up limit and EMIOS_CADR value to the EMIOS_CBDR register.
Figure 28-45 shows two cycles of a center-aligned PWM signal. Both A1 and B1 register values are
changing within the same cycle, which allows to vary at the same time the duty cycle and dead-time values.
Selected
Time
Write to A2
Write to B2
Write to B2
Write to A2
0x000001
0x000005
0x000006
0x000015
A1 Value
A2 Value
0x000020
0x000015
Selected Counter = 2
A1/B1 Load Signal
0x000020 0x000016
0x000016
Cycle n Cycle n + 1 Cycle n +2
B1 Value
0x000004
B2 Value
0x000004 0x0000060x000005
0x000005 0x000006
Counter Bus
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