NXP Semiconductors PXN2020 - Page 869

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-47
Figure 28-45. Output PWMCB with Lead Dead-Time Insertion
When operating with trailing edge dead-time insertion, the first match between A1 and the selected time
base sets the output flip-flop to the value of the EDPOL bit and sets the internal counter to 0x00_0001. In
the second match between register A1 and the selected time base, the internal counter is set to 0x00_0001
and B1 matches are enabled. When the match between register B1 and the selected time base occurs, the
output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously.
EDPOL = 1
Internal
Internal Counter is
Dead-Time
A1 Value
A2 Value
B1 Value
B2 Value
Selected
0x000002 0x000004
0x000002 0x000004
0x000015
0x000015
0x000013
0x000013
0x000001
0x000002
0x000004
0x000015
0x000013
0x000020
Output Flip-Flop
FLAG Set Event
0x000001
Counter Bus
Time
Time
Time Base
Dead-Time
Set to 1 on A1 Match
Write to B2
Write to A2