NXP Semiconductors PXN2020 - Page 870

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-48 Freescale Semiconductor
Figure 28-46. Output PWMCB with Trail Dead-Time Insertion
FLAG can be generated in the trailing edge of the output PWM signal when MODE[5] is cleared, or in
both edges when MODE[5] is set. If subsequent matches occur on comparators A and B, the PWM pulses
continue to be generated regardless of the state of the FLAG bit.
NOTE
In OPWMCB mode, FORCMA and FORCMB do not have the same
behavior as a regular match. Instead they force the output flip-flop to
constant value, which depends on the selected dead-time insertion mode,
lead or trail and the value of the EDPOL bit.
FORCMA has different behaviors depending on the selected dead time insertion mode, lead or trail. In lead
dead-time insertion FORCMA force a transition in the output flip-flop to the opposite of EDPOL. In trail
dead-time insertion the output flip-flop is forced to the value of EDPOL bit.
If FORCMB bit is set, the output flip-flop value depends on the selected dead-time insertion mode. In lead
dead time insertion FORCMB forces the output flip-flop to transition to EDPOL bit value. In trail
dead-time insertion the output flip-flop is forced to the opposite of EDPOL bit value.
NOTE
FORCMA bit set does not set the internal time-base to 0x00_0001 as a
regular A1 match.
EDPOL = 1
Internal
Internal Counter is
Dead-Time
A1 Value
A2 Value
B1 Value
B2 Value
Selected
0x000002 0x000004
0x000002 0x000004
0x000015
0x000015
0x000013
0x000013
0x000001
0x000002
0x000004
0x000015
0x000013
0x000020
Output Flip-Flop
FLAG Set Event
0x000001
Counter Bus
Time
Time
Time Base
Dead-Time
Set to 1 on A1 Match
Write to B2
Write to A2