Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-52 Freescale Semiconductor
The output pin transitions are based on the negedges of the A1 and B1 match signals. Figure 28-48 shows
in cycle(n + 1) the value of the A1 register being set to zero. In this case, the match posedge is used instead
of the negedge to transition the output flip-flop.
Figure 28-49 shows the channel operation for 0% duty cycle. Note that the A1 match posedge signal
occurs at the same time as the B1 = 8 negedge signal. In this case A1 match has precedence over B1 match,
causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal.
Figure 28-49. OPWMB Mode with 0% Duty Cycle
Figure 28-50 shows the operation of the OPWMB mode with the output disable signal asserted. The output
disable forces a transition in the output pin to the EDPOL bit value. After deassertion, the output disable
allows the output pin to transition at the following A1 or B1 match. The output disable does not modify
the flag bit behavior. There is one system clock delay between the assertion of the output disable signal
and the transition of the output pin to EDPOL.
1
4
A1 Match Negedge
A1 Value 0x000004
A1 Match
Output Pin
Selected
Time
B1 Match
B1 Value 0x000008
Clock
Prescaler
A2 Value 0x000000
0x000000
A1 Match Posedge Detection
1
8
FLAG Bit Set
EDPOL = 0
A1 Match Negedge
B1 Match Negedge
A1 Match Posedge
Detection
Detection
Detection
Cycle n
Cycle n +1
Write to A2
Detection
8
Counter Bus
A1 Match Negedge Detection
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