NXP Semiconductors PXN2020 - Page 878

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-56 Freescale Semiconductor
Figure 28-52. OPWMT Example{statement}
Figure 28-53 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and
0% duty cycle.
Figure 28-53. OPWMT with 0% Duty Cycle
Figure 28-54 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and
100% duty cycle.
0x0011FF
0x001000
0x000000
Selected Counter Bus
Time
Output Flip-Flop
A1 Value
1
write to B2
0x000400
B1 Value
B2 Value
2
0x000700
Match B1
write to A1
0xxxxxxx
0x000400
0x001000
0x000700
and B2
0x001000
Match A1
Match B1 Match A1
Notes:
1. EMIOS_CADR[n] = A1
2. EMIOS_CBDR[n] = B2 for write, B1 for read
0x000700
A2 Value
0x000500
0x000500
FLAG Pin/Register
Match A2
Match A2
0x0011FF
0x001000
0x000000
Selected Counter Bus
Time
Output Flip-Flop
A1 Value1
write to B2
0x000400
B1 Value
B2 Value2
0x000400
Match B1
write to A1
0xxxxxxx
0x000400
0x001000
and B2
0x001000
Match A1
Match B1 Match A1
Notes:
1. EMIOS_CADR[n] = A1
2. EMIOS_CBDR[n] = B2 for write, B1 for read
0x000400
A2 Value
0x000500
0x000500
FLAG Pin/Register
Match A2
Match A2