Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-5
The offset address ranges 0x0060–0x047F and 0x0880–0x097F are occupied by two separate embedded
memories. These two ranges are completely occupied by RAM (1 KB and 256 bytes, respectively) when
FlexCAN is configured with 64 MBs. Furthermore, if the BCC bit in CANx_MCR is negated, then the
whole Rx individual mask registers address range (0x0880–0x097F) is considered reserved space.
Table 29-1. FlexCAN Memory Map
Offset from
FlexCAN_BASE
(FlexCAN_A: 0xFFFC_0000
FlexCAN_B: 0xFFFC_4000
FlexCAN_C: 0xFFFC_8000
FlexCAN_D: 0xFFFC_C000
FlexCAN_E: 0xFFFD_0000
FlexCAN_F: 0xFFFD_4000)
Register Access Reset Value Section/Page
0x0000 CANx_MCR—Module Configuration R/W 0x9890_000F 29.3.4.1/29-11
0x0004 CANx_CTRL—Control Register R/W 0x0000_0000 29.3.4.2/29-14
0x0008 CANx_TIMER—Free-Running Timer R/W 0x0000_0000 29.3.4.3/29-17
0x000C Reserved
0x0010 CANx_RXGMASK—Rx Global Mask R/W 0xFFFF_FFFF 29.3.4.4.1/29-18
0x0014 CANx_RX14MASK—Rx Buffer 14 Mask R/W 0xFFFF_FFFF 29.3.4.4.2/29-19
0x0018 CANx_RX15MASK—Rx Buffer 15 Mask R/W 0xFFFF_FFFF 29.3.4.4.3/29-19
0x001C CANx_ECR—Error Counter Register R/W 0x0000_0000 29.3.4.5/29-20
0x0020 CANx_ESR—Error and Status Register R/W 0x0000_0000 29.3.4.6/29-21
0x0024 CANx_IMASK2—Interrupt Masks 2 R/W 0x0000_0000 29.3.4.7/29-23
0x0028 CANx_IMASK1—Interrupt Masks 1 R/W 0x0000_0000 29.3.4.8/29-24
0x002C CANx_IFLAG2—Interrupt Flags 2 R/W 0x0000_0000 29.3.4.9/29-24
0x0030 CANx_IFLAG1—Interrupt Flags 1 R/W 0x0000_0000 29.3.4.10/29-25
0x0034–0x007F Reserved
0x0080–0x017F MB0–MB15—Message Buffers R/W —
1
1
Please refer to the register definition.
29.3.2/29-7
0x0180–0x027F MB16–MB31—Message Buffers R/W —
1
0x0280–0x047F MB32–MB63—Message Buffers R/W —
1
0x0480–0x087F Reserved
0x0880–0x08BF CANx_RXIMR0–CANx_RXIMR15—Rx Individual
Mask Registers
R/W 0x0000_0000 29.3.4.11/29-26
0x08C0–0x08FF CANx_RXIMR16–CANx_RXIMR31—Rx Individual
Mask Registers
R/W 0x0000_0000
0x0900–0x097F CANx_RXIMR32–CANx_RXIMR63—Rx Individual
Mask Registers
R/W 0x0000_0000