NXP Semiconductors PXN2020 - Page 894

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-10 Freescale Semiconductor
data from the FIFO (the oldest frame received and not read yet). The region 0x90–0xDC is reserved for
internal use of the FIFO engine. The region 0xE0–0xFC contains an eight-entry ID table that specifies
filtering criteria for accepting frames into the FIFO. Figure 29-4 shows the three different formats that the
elements of the ID table can assume, depending on the IDAM field of the CANx_MCR. Note that all
elements of the table must have the same format. See Section 29.4.6, Rx FIFO, for more information.
012345678910111213141516171819202122232425262728293031
0x80
SRR
IDE
RTR
LENGTH TIME STAMP
0x84
ID (Extended/Standard) ID (Extended)
0x88 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3
0x8C Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
0x90
Reservedto
0xDC
0xE0 ID Table 0
0xE4 ID Table 1
0xE8 ID Table 2
0xEC ID Table 3
0xF0 ID Table 4
0xF4 ID Table 5
0xF8 ID Table 6
0xFC ID Table 7
Figure 29-3. Rx FIFO Structure
A
R
E
M
E
X
T
RXIDA
(Standard = 29–19, Extended = 29–1)
B
R
E
M
E
X
T
RXIDB_0
(Standard = 29–19, Extended = 29–16)
R
E
M
E
X
T
RXIDB_1
(Standard = 13–3, Extended = 13–0)
C
RXIDC_0
(Std/Ext = 31–24)
RXIDC_1
(Std/Ext = 23–16)
RXIDC_2
(Std/Ext = 15–8)
RXIDC_3
(Std/Ext = 7–0)
Figure 29-4. ID Table 0–7