NXP Semiconductors PXN2020 - Page 978

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-52 Freescale Semiconductor
It is recommended that the baud rate is the same for all transfers made while using the continuous SCK.
Switching clock polarity between frames while using continuous SCK can cause errors in the transfer.
Continuous SCK operation is not guaranteed if the DSPI is put into halt mode or module disable mode.
Enabling continuous SCK disables the PCS to SCK delay and the delay after transfer (T
DT
) is fixed at one
T
SCK
cycle. When TSB configuration is enabled the T
DT
is programmable to a minimum of 1xT
SCK
cycles
by configuring PDT and DT values in the respective CTAR register. Figure 30-36 shows timing diagram
for continuous SCK format with continuous selection disabled.
Enabling continuous SCK disables the PCS to SCK delay and the after SCK delay. The delay after transfer
is fixed at one SCK cycle. Figure 30-36 shows timing diagram for continuous SCK format with continuous
selection disabled.
Figure 30-36. Continuous SCK Timing Diagram (CONT = 0)
If the CONT bit in the TX FIFO entry is set or the DCONT in the DSPI_DSICR is set, PCS remains
asserted between the transfers. Under certain conditions, SCK can continue with PCS asserted, but with
no data being shifted out of SOUT (SOUT pulled high). This can cause the slave to receive incorrect data.
Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO.
• Continuous SCK with CONT bit set and entering STOPPED state (refer to Section 30.4.2, Start
and Stop of DSPI Transfers).
• Continuous SCK with CONT bit set and entering halt mode or module disable mode.
Figure 30-37 shows timing diagram for continuous SCK format with continuous selection enabled.
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
t
DT
t
DT
= 1 SCK.
Master SIN