NXP Semiconductors PXN2020 - Page 850

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-28 Freescale Semiconductor
The input pulse period is calculated by subtracting the value in B1 from A2.
Figure 28-22 shows how the unified channel can be used for input period measurement.
Figure 28-22. Input Period Measurement Example
Figure 28-23 shows the A1 and B1 register updates when EMIOS_CADR[n] and EMIOS_CBDR[n] read
operations are performed. When EMIOS_CADR[n] read occurs, the content of A1 is transferred to B1 thus
providing coherent data in A2 and B1 registers. Transfers from B2 to B1 are then blocked until
EMIOS_CBDR[n] is read. After EMIOS_CBDR[n] is read, register A1 content is transferred to register
B1 and the transfers from B2 to B1 are re-enabled to occur at the transfer edges, which is the leading edge
in the Figure 28-23 example.
Figure 28-23. A1 and B1 Updates at EMIOS_CADR[n] and EMIOS_CBDR[n] Reads
0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0
Selected
Counter Bus
FLAG
Set Event
A
A2 (Captured)
Value
2
0xxxxxxx 0x001000 0x001250 0x0016A0
Notes:
1
After input filter
2
EMIOS_CADR[n] = A2
Input Signal
1
EDPOL = 1 A A
B1 Value
3
0xxxxxxx 0xxxxxxx 0x001000 0x001250
0xxxxxxx 0x001000 0x001250 0x0016A0
B2 (Captured)
Value
3
EMIOS_CBDR[n] = B1
0xxxxxxx 0xxxxxxx 0x001000 0x001250 A1 Value
0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0
Selected
Counter Bus
FLAG
Set Event
AAA
A2 (Captured)
Value
2
0xxxxxxx
Notes:
1
After input filter
2
EMIOS_CADR[n] = A2
Input Signal
1
EDPOL = 1
B1 Value
3
0x001525
0xxxxxxx
0xxxxxxx
0x001000 0x001250 0x0016A0
B2 (Captured)
Value
3
EMIOS_CBDR[n] = B1
0xxxxxxx 0x001250
A1 Value
0x001000
Read EMIOS_CADR[n] Read EMIOS_CBDR[n]
0x001100 0x001250
0x001000
0x001000 0x001250