Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-44 Freescale Semiconductor
Figure 28-42. OPWFMB Mode with Active Output Disable
The output disable has a synchronous operation, meaning that the assertion of the output disable input pin
causes the channel output flip-flop to transition to EDPOL at the next system clock cycle. If the output
disable input is deasserted the output pin transition at the following A1 or B1 match.
In Figure 28-42 it is assumed that the output disable input is enabled and selected for the channel. Refer
to Section 28.3.2.8, eMIOS200 Control Register (EMIOS_CCR[n]), for a description of how the ODIS
and ODISSL bits enable and select the output disable inputs.
The FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on comparators A or B respectively. Similar to a B1 match FORCMB sets the
internal counter to 0x00_0001. The FLAG bit is not set by the FORCMA or FORCMB bits being asserted.
Figure 28-43 shows the generation of 100% and 0% duty cycle signals. It is assumed EDPOL = 0 and the
resultant prescaler value is 1. Initially, A1 = 0x00_0008 and B1 = 0x00_0008. In this case, the B1 match
has precedence over the A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This
cycle corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value
greater or equal to B1.
Cycle n Cycle n +1 Cycle n +2
A1 Value
B1 Value
B2 Value
0x000008
0x000002
0x000006
0x000008
0x000001
Internal Counter
0x000004
0x000006
A2 Value
0x000002 0x000004 0x000006
0x000002
0x000004
0x000006
0x000008 0x000006
Output Pin
Write to B2
Match A1 Match B1
Match B1
Output Disable
Due to B1 Match
FLAG Set Event
Cycle n –1
Time
Write to A2
Match A1
Write to A2 Match B1
EDPOL = 0
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