EasyManuals Logo

ST STM8S Reference Manual

ST STM8S
449 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #19 background imageLoading...
Page #19 background image
RM0016 List of figures
Doc ID 14587 Rev 8 19/449
List of figures
Figure 1. Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 2. Stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4. Default stack model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. Customized stack model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6. Flash memory and data EEPROM organization on low density STM8S . . . . . . . . . . . . . . 38
Figure 7. Flash memory and data EEPROM organization on medium density STM8S and STM8A. 39
Figure 8. Flash memory and data EEPROM organization high density STM8S and STM8A . . . . . . 40
Figure 9. UBC area size definition on low density STM8S devices . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 10. UBC area size definition on medium density STM8S
and STM8A with up to 32 Kbytes of Flash program memory . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11. UBC area size definition on high density STM8S and
STM8A with up to 128 Kbytes of Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. SWIM pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 13. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 14. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 15. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 16. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 17. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 18. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 19. VDD/VDDIO voltage detection: POR/BOR threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 20. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 21. HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 22. Clock switching flowchart (automatic mode example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 23. Clock switching flowchart (manual mode example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 24. GPIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 25. AWU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 26. Beep block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 27. Independent watchdog (IWDG) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 28. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 29. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 30. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 31. TIM1 general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 32. Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 33. 16-bit read sequence for the counter (TIM1_CNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 34. Counter in up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 35. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 142
Figure 36. Counter update event when ARPE = 1 (TIM1_ARR preloaded). . . . . . . . . . . . . . . . . . . . 142
Figure 37. Counter in down-counting mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 38. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 144
Figure 39. Counter update when ARPE = 1 (ARR preloaded), with prescaler = 1 . . . . . . . . . . . . . . 144
Figure 40. Counter in center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 41. Counter timing diagram, f
CK_CNT
= f
CK_PSC
, TIM1_ARR = 06h, ARPE = 1 . . . . . . . . . . . 146
Figure 42. Update rate examples depending on mode and TIM1_RCR register settings . . . . . . . . . 148
Figure 43. Clock/trigger controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 44. Control circuit in normal mode, f
CK_PSC
= f
MASTER
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 45. TI2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 46. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table of Contents

Other manuals for ST STM8S

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM8S and is the answer not in the manual?

ST STM8S Specifications

General IconGeneral
BrandST
ModelSTM8S
CategoryMicrocontrollers
LanguageEnglish

Related product manuals