RM0016 Serial peripheral interface (SPI)
Doc ID 14587 Rev 8 261/449
Handling data transmission and reception
The TXE flag (Tx buffer empty) is set when the data is transferred from the Tx buffer to the
shift register. It indicates that the internal Tx buffer is ready to be loaded with the next data.
An interrupt can be generated if TXIE bit in the SPI_ICR register is set.
Note: The software must ensure that TXE flag is set to 1 before attempting to write into the Tx
buffer. Otherwise, it will overwrite the data which was previously written in the Tx buffer.
The RXNE flag (Rx buffer not empty) is set on the last sampling clock edge, when the data
is transferred from the shift register to the Rx buffer. It indicates that a data is ready to be
read from the SPI_DR register. An interrupt can be generated if RXIE bit in the SPI_ICR
register is set. Clearing the RXNE bit is performed by reading the SPI_DR register.
In some configurations, the BSY flag can be used during the last data transfer to wait until
the completion of the transfer.
Full Duplex Transmit and receive procedure in master or slave mode
(BDM=0 and RXONLY = 0)
1. Enable the SPI by setting the SPE bit
2. Write the first data to be transmitted in the SPI_DR register (this clears the TXE flag).
3. Wait until TXE = 1 and write the second data to be transmitted. Then wait until RXNE =
1 and read the SPI_DR to get the first received data (this clears the RXNE bit). Repeat
this operation for each data to be transmitted/received until the n-1 received data.
4. Wait until RXNE = 1 and read the last received data.
5. Wait until TXE = 1 and then wait until BSY = 0 before disabling the SPI.
This procedure can also be implemented using dedicated interrupt subroutines launched at
each rising edge of RXNE or TXE flags.
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