RM0016 Universal asynchronous receiver transmitter (UART)
Doc ID 14587 Rev 8 331/449
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared
detector and outputs the received NRZ serial bit stream to UART. The decoder input is
normally HIGH (marking state) in the idle state. The transmit encoder output has the
opposite polarity to the decoder input. A start bit is detected when the decoder input is low.
● IrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the UART is
sending data to the IrDA encoder), any data on the IrDA receive line will be ignored by
the IrDA decoder and if the Receiver is busy (UART is receiving decoded data from the
UART), data on the TX from the UART to IrDA will not be encoded by IrDA. While
receiving data, transmission should be avoided as the data to be transmitted could be
corrupted.
● A ’0’ is transmitted as a high pulse and a ’1’ is transmitted as a ’0’. The width of the
pulse is specified as 3/16th of the selected bit period in normal mode (see Figure 128).
● The SIR decoder converts the IrDA compliant receive signal into a bit stream for the
UART.
● The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
● The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when idle.
● The IrDA specification requires the acceptance of pulses greater than 1.41 us. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in UART_PSCR). Pulses of width less than 1 PSC period are always
rejected, but those of width greater than one and less than two periods may be
accepted or rejected, those greater than 2 periods will be accepted as a pulse. The
IrDA encoder/decoder doesn’t work when PSC=0.
● The receiver can communicate with a low-power transmitter.
● In IrDA mode, the STOP bits in the UART_CR2 register must be configured to “1 stop
bit”.
IrDA low-power mode
The IrDA can be used either in normal mode or in Low Power mode. The Low Power mode
is selected by setting the IRLP bit in UART_CR5 register.
Transmitter:
In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the
width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz.
Generally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode
programmable divisor divides the system clock to achieve this value.
Receiver:
Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the
UART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if
its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in
UART_PSCR).
Note: 1 A pulse of width less than two and greater than one PSC period(s) may or may not be
rejected.
2 The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and reception (IrDA
is a half duplex protocol).
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