RM0016 Controller area network (beCAN)
Doc ID 14587 Rev 8 373/449
Scalable width
To optimize and adapt the filters to the application needs, each filter bank can be scaled
independently. Depending on the filter scale a filter bank provides:
– One 32-bit filter for the STDID[10:0] / EXID[28:18], IDE, EXID[17:0] and RTR bits.
– Two 16-bit filters for the STDID[10:0] / EXID[28:18], RTR and IDE bits.
– Four 8-bit filters for the STDID[10:3] / EXID[28:21] bits. The other bits are
considered as don’t care.
– One 16-bit filter and two 8-bit filters for filtering the same set of bits as the 16 and
8-bit filters described above.
Refer to Figure 147 through Figure 150.
Furthermore, the filters can be configured in mask mode or in identifier list mode.
Mask mode
In mask mode the identifier registers are associated with mask registers specifying which
bits of the identifier are handled as “must match” or as “don’t care”.
Identifier list mode
In identifier list mode, the mask registers are used as identifier registers. Thus instead of
defining an identifier and a mask, two identifiers are specified, doubling the number of single
identifiers. All bits of the incoming identifier must match the bits specified in the filter
registers.
Filter bank scale and mode configuration
The filter banks are configured by means of the corresponding CAN_FCRx register. To
configure a filter bank this must be deactivated by clearing the FACT bit in the CAN_FCRx
register. The filter scale is configured by means of the FSC[1:0] bits in the corresponding
CAN_FCRx register. The identifier list or identifier mask mode for the corresponding
Mask/Identifier registers is configured by means of the FMLx and FMHx bits in the
CAN_FMRx register. The FMLx bit defines the mode for the lower half (registers
CAN_FxR1-4), and the FMHx bit the mode for the upper half (registers CAN_FxR5-8) of
filter bank x. Refer to Figure 147 through Figure 150 for details.
Examples:
– If filter bank 1 is configured as two 16-bit filters, then the FML1 bit defines the
mode of the CAN_F1R3 and CAN_F1R4 registers and the FMH1 bit defines the
mode of the CAN_F1R7 and CAN_F1R8 registers.
– If filter bank 1 is configured as four 8-bit filters, then the FML1 bit defines the mode
of the CAN_F1R2 and CAN_F1R4 registers and the FMH1 bit defines the mode of
the CAN_F1R6 and CAN_F1R8 registers.
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