RM0016 Interrupt controller (ITC)
Doc ID 14587 Rev 8 61/449
TRAP interrupt occurs. The corresponding vector is then loaded in the PC register and bits
I1 and I0 of the CCR register are set to disable interrupts (level 3).
● TRAP (non-maskable software interrupt)
This software interrupt source is serviced when the TRAP instruction is executed. It is
serviced as a TLI according to the flowchart shown in Figure 13.
A TRAP interrupt does not allow the processor to exit from Halt mode.
● RESET
The RESET interrupt source has the highest STM8 software and hardware priorities.
This means that all the interrupts are disabled at the beginning of the reset routine.
They must be re-enabled by the RIM instruction (see Table 11: Dedicated interrupt
instruction set).
A RESET interrupt allows the processor to exit from Halt mode.
See RESET chapter for more details on RESET interrupt management.
● TLI (top level hardware interrupt)
This hardware interrupt occurs when a specific edge is detected on the corresponding
TLI input.
Caution: A TRAP instruction must not be used in a TLI service routine.
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