LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller
Version 1.0 4-21
4.5.3.1.1 Horizontal Timing Restrictions
The LCD DMA requests new data at the start of a horizontal display line. Some time must
be allowed for the DMA transfer and for the data to propagate down the FIFO path in the
LCD interface. The data path latency forces some restrictions on the usable minimum values
for horizontal porch width in STN Mode.
The minimum values are HSW = 2 and HBP = 2.
Single Panel Mode:
• HSW = 3
• HBP = 5
• HFP = 5
• Panel Clock Divisor (PCD) = 1 (CLCDCLK/3)
Dual Panel Mode:
• HSW = 3
• HBP = 5
• HFP = 5
• PCD = 5 (CLCDCLK/7)
If sufficient time is given at the start of the line (for example, setting HSW = 6, HBP = 10),
data will not get corrupted for PCD = 4 (minimum value).
NOTE: CLCDCLK is a separate clock provided by the Reset Clock and Power Controller (RCPC).
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