Sharp LH79524 - System Clock Prescaler Register (SYSCLKPRE); Table 13-16. SYSCLKPRE Register; Table 13-17. SYSCLKPRE Fields; Table 13-18. SYSCLKPRE Register Values

LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller
Version 1.0 13-17
13.2.2.7 System Clock Prescaler Register (SYSCLKPRE)
HCLK is the System Clock. This register allows a divisor to be programmed that is used to
divide the system PLL frequency to derive HCLK. The prescaled HCLK frequency is
defined by:
Following reset, the prescaler is programmed to divide by 30. Table 13-18 shows example
values for HDIV.
Table 13-16. SYSCLKPRE Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// HDIV
RESET 0000000000001111
RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
ADDR 0xFFFE2000 + 0x18
Table 13-17. SYSCLKPRE Fields
BITS NAME DESCRIPTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3:0 HDIV
HCLK Divisor Program with the divisor for the HCLK prescaler. All
HDIV combinations are valid except 0b0000.
Table 13-18. SYSCLKPRE Register Values
HDIV DIVISOR ƒ(HCLK)
0b0000 — Invalid
0b0001 2 ƒ(System PLL)/2
0b0010 4 ƒ(System PLL)/4
0b0011 6 ƒ(System PLL)/6
0b0100 8 ƒ(System PLL)/8
0b0101 10 ƒ(System PLL)/10
:: :
0b1111 (default) 30 ƒ(System PLL)/30
ƒ(HCLK) ƒ
ƒ(SystemPLL)
2 HDIV×
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