LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller
Version 1.0 4-3
4.2 CLCDC Features
• Supported LCD Panels
– Active-matrix TFT, HR-TFT and AD-TFT panels, with up to 16-bit bus interface
(LH79524) or 12-bit bus (LH79525)
– Single-panel monochrome STN panels, with 4-bit and 8-bit bus interfaces
– Dual-panel monochrome STN panels, with 4-bit and 8-bit bus interface per panel
– Single-panel color STN panels, with an 8-bit bus interface (LH79524 only)
– Dual-panel color STN panels, with 8-bit bus interface per panel (LH79524 only)
• Resolution up to 1024 × 1024 dots per inch (DPI)
• Additional Features
– Programmable timing for different display panels
– 256-entry, 16-bit palette RAM physically arranged as a 128 × 32-bit RAM
– AC bias signal for TFT panels and a data-enable signal for TFT panel
The following parameters can be programmed in the CLCDC:
• Horizontal front and back porch width
• Horizontal synchronization pulse width
• Number of pixels per line
• Vertical front and back porch width
• Vertical synchronization pulse width
• Number of horizontal lines per panel
• Number of panel data clocks per line
• Programmable signal polarities, active HIGH or active LOW
• AC panel bias
• Panel data clock frequency (LCDDCLK)
• Bits-per-pixel
• Little-endian, big-endian, and WinCE
TM
data formatting
• Interrupt generation.
4.3 Theory of Operation
The CLCDC is an AMBA master-slave module that connects to the AHB. Figure 4-3
is a detailed block diagram of the CLCDC. Packets of pixel-coded data are sent, via the
AHB interface, to two independently programmable, 32-bit-wide DMA FIFOs. Each FIFO
is 16 words deep by 32 bits wide. In Single Panel STN Mode, the LCD DMA FIFOs appear
as a single FIFO of twice the size. The buffered pixel-coded data is then unpacked via a
pixel serializer.
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