Sharp LH79524 - System PLL Control Register (SYSPLLCTL); Table 13-52. SYSPLLCTL Register; Table 13-53. SYSPLLCTL Fields

LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller
Version 1.0 13-33
13.2.2.22 System PLL Control Register (SYSPLLCTL)
This register controls the System PLL frequency. System PLL frequency is calculated by:
The maximum System PLL frequency is 304.819 MHz.
Table 13-52. SYSPLLCTL Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// ///
SYSFRANGE
SYSPREDIV SYSLOOPDIV
RESET 0010000001000101
RW RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE2000 + 0xC0
Table 13-53. SYSPLLCTL Fields
BITS NAME DESCRIPTION
31:14 /// Reserved Reading returns 0. Write the reset value.
13 /// Reserved Reading returns 0. Write 1 only.
12 SYSFRANGE
System PLL Output Frequency Range Select
1 = 100 MHz to 304.819 MHz (best jitter performance achieved)
0 = 20 MHz to 100 MHz
11:6 SYSPREDIV
System PLL Pre-Divider Prescales the System PLL Reference
clock. The divisor chosen must satisfy the equation:
(System Clock Oscillator frequency) ÷ (SYSPREDIV) ≥ 5 MHz
5:0 SYSLOOPDIV
System PLL Loop-Divider Prescales the System PLL Feedback
clock. The divisor can be programmed from 1 to 63.
SystemPLLfrequencySystem
SystemClockOscillatorFrequency SYSLOOPDIV×
SYSPREDIV
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