Sharp LH79524 - Peripheral Clock Select Register 0 (PCLKSEL0); Table 13-28. PCLKSEL0 Register; Table 13-29. PCLKSEL0 Fields

Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide
13-22 Version 1.0
13.2.2.12 Peripheral Clock Select Register 0 (PCLKSEL0)
This register allows selection of the clock source for the UARTs.
Table 13-28. PCLKSEL0 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
UART2 UART1 UART0
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW
ADDR 0xFFFE2000 + 0x30
Table 13-29. PCLKSEL0 Fields
BITS NAME DESCRIPTION
31:3 /// Reserved Reading returns 0. Write the reset value.
2UART2
UART2 Clock Source
1 = System Clock (HCLK)
0 = Crystal oscillator output
1UART1
UART1 Clock Source
1 = System Clock (HCLK)
0 = Crystal oscillator output
0UART0
UART0 Clock Source
1 = System Clock (HCLK)
0 = Crystal oscillator output