LH79524/LH79525 User’s Guide Boot Controller
Version 1.0 3-3
Table 3-1. Boot Configuration for Silicon Version A.0
PC[7:4] DEVICE TYPE DATA BUS WIDTH CONTROL
0x0 NOR Flash or SRAM 16-bit nBLEx LOW for Reads
0x1 NOR Flash or SRAM 16-bit nBLEx HIGH for Reads
0x2 NOR Flash or SRAM 8-bit nBLEx LOW for Reads
0x3 NOR Flash or SRAM 8-bit nBLEx HIGH for Reads
0x4 NAND Flash (Small Block) 8-bit 3-byte Address
0x5 NAND Flash (Small Block) 8-bit 4-byte Address
0x6 NAND Flash (Small Block) 8-bit 5-byte Address
0x7 NAND Flash (Small Block) 16-bit 3-byte Address
0x8 NOR Flash or SRAM 32-bit nBLEx LOW for Reads
0x9 NOR Flash or SRAM 32-bit nBLEx HIGH for Reads
0xA RESERVED RESERVED RESERVED
0xB RESERVED RESERVED RESERVED
0xC NAND Flash (Small Block) 16-bit 4-byte Address
0xD NAND Flash (Small Block) 16-bit 5-byte Address
0xE RESERVED RESERVED RESERVED
0xF RESERVED RESERVED RESERVED
Table 3-2. Boot Configuration for Silicon Version A.1
PC[7:4] DEVICE TYPE DATA BUS WIDTH CONTROL
0x0 NOR Flash or SRAM 16-bit nBLEx LOW for Reads
0x1 NOR Flash or SRAM 16-bit nBLEx HIGH for Reads
0x2 NOR Flash or SRAM 8-bit nBLEx LOW for Reads
0x3 NOR Flash or SRAM 8-bit nBLEx HIGH for Reads
0x4 NAND Flash (Small Block) 8-bit 3-byte Address
0x5 NAND Flash (Small Block) 8-bit 4-byte Address
0x6 NAND Flash (Large Block) 8-bit 4/5-byte Address
0x7 NAND Flash (Small Block) 16-bit 3-byte Address
0x8 NOR Flash or SRAM 32-bit nBLEx LOW for Reads
0x9 NOR Flash or SRAM 32-bit nBLEx HIGH for Reads
0xA RESERVED RESERVED RESERVED
0xB RESERVED RESERVED RESERVED
0xC NAND Flash (Small Block) 16-bit 4-byte Address
0xD NAND Flash (Large Block) 16-bit 4/5-byte Address
0xE I
2
C——
0xF UART — —
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