Sharp LH79524 - Chapter 5 - Direct Memory Access Controller; Table 5-4. SOURCELO Register; Table 5-5. SOURCELO Fields; Table 5-6. SOURCEHI Register

Direct Memory Access Controller LH79524/LH79525 User’s Guide
5-6 Version 1.0
5.2.2 Register Definitions
5.2.2.1 Source Base Registers (SOURCELO and SOURCEHI)
The two 16-bit Source Base Registers contain the 32-bit source base address for the next
DMA transfer. When the DMA Controller is enabled, the contents of the Source Base Reg-
isters load into the Current Source Address Register.
Table 5-4. SOURCELO Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD SOURCELO
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR DATASTREAM x BASE + 0x000
Table 5-5. SOURCELO Fields
BITS NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:0 SOURCELO
Low Order Source Address This field contains the lower 16-bits
of the address for the source of data for the next DMA transfer.
Table 5-6. SOURCEHI Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD SOURCEHI
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR DATASTREAM x BASE + 0x004
Table 5-7. SOURCEHI Fields
BITS NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:0 SOURCEHI
High Order Source Address This field contains the upper 16-bits
of the address for the source of data for the next DMA transfer.