Sharp LH79524 - Control Status Register 1 for out EP1 and EP2 (OUTSCSR1); Table 17-36. OUTCSR1 Register; Table 17-37. OUTCSR1 Fields

LH79524/LH79525 User’s Guide Universal Serial Bus Device
Version 1.0 17-27
17.2.3.7 Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1)
OUTCSR1 provides control and status bits for transfers through the currently-selected
OUT endpoint
.
Table 17-36. OUTCSR1 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
CLRTOG
SENT_STALL
SEND_STALL
FIFO_FLUSH
DATAERROR
OVERRUN
FIFOFull
OUT_PKT_RDY
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RW RW RW RW RO RW RO RW
ADDR
0xFFFF5000 + 0x050
(with the INDEX register set to 1 or 2)
Table 17-37. OUTCSR1 Fields
BITS NAME FUNCTION
31:8
/// Reserved Reading returns 0. Write the reset value.
7 CL_DATATOG
Clear Data Toggle Sequence Bit The Serial Interface Engine (SIE)
tracks the Data PID sequence toggle received for USB transactions
with multiple data packets. An error condition that requires the USB
transaction to be re-synchronized, this bit should be programmed to 1
to reset the data toggle so that the SIE expects a DATA0 packet iden-
tifier on the next transfer. Software writes a 1 to this bit to clear the data
toggle bit. The USB block programs this bit to 0 when a read is received
from the USB Host.
1 = The data toggle sequence bit is reset to DATA0
0 = No effect
6 SENT_STALL
Stall Handshake Sent The USB block sets this bit to 1 when an OUT
token is ended with a STALL handshake from the USB Host. The USB
block issues a stall handshake if the Host sends more than MAXP data
for the OUT token. Software clears this bit by writing a 0.
1 = OUT token ended with a STALL handshake
0 = No STALL handshake received
5 SEND_STALL
Send Stall Handshake Software programs a 1 to this bit to issue a
STALL handshake to the USB Host.
1 = Issue STALL handshake to USB Host
0 = End STALL condition