LH79524/LH79525 User’s Guide Vectored Interrupt Controller
Version 1.0 18-15
18.2.2.13 Interrupt Test Output Register (ITOP)
Reading the ITOP register returns the status of the IRQ and FIQ interrupt request outputs
from the VIC to the ARM exception-handling circuitry.
Table 18-27. ITOP Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// VF VI ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFFF000 + 0x30C
Table 18-28. ITOP Fields
BIT NAME DESCRIPTION
31:8
///
Reserved Reading returns 0. Write the reset value.
7VI
VIC IRQ Output Status
1 = an IRQ interrupt request to the ARM core is asserted.
0 = an IRQ interrupt request to the ARM core is not asserted.
6VF
VIC FIQ Output Status
1 = an FIQ interrupt request to the ARM core is asserted.
0 = an FIQ interrupt request to the ARM core is not asserted.
5:0
///
Reserved Reading returns 0. Write the reset value.