Sharp LH79524 - Multiplexing Control 25 Register (MUXCTL25); Table 11-72. MUXCTL25 Register

I/O Configuration LH79524/LH79525 User’s Guide
11-54 Version 1.0
11.2.2.36 Multiplexing Control 25 Register (MUXCTL25)
The MUXCTL25 Register allows software to configure a number of LH79524/LH79525 pins.
Table 11-72. MUXCTL25 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD AN6 AN7 AN5 AN8 AN2 AN9 AN4 AN3
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0xC0
Table 11-73. MUXCTL25 Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Writing to these BIT has no effect. Reading returns 0.
15:14 AN6
AN6/PJ7/INT7 Assignment
00 = AN6
01 = PJ7
10 = INT7
11 = Reserved
13:12 AN7
AN7/PJ6/INT6 Assignment
00 = AN7
01 = PJ6
10 = INT6
11 = Reserved
11:10 AN5
AN5/PJ5/INT5 Assignment
00 = AN5
01 = PJ5
10 = INT5
11 = Reserved
9:8 AN8
AN8/PJ4 Assignment
00 = AN8
01 = PJ4
10 = Reserved
11 = Reserved
7:6 AN2
AN2/LL/Y+/PJ3 Assignment
00 = AN2/LL/Y+
01 = PJ3
10 = Reserved
11 = Reserved