Sharp LH79524 - Raw Interrupt Status Register (RIS); Table 10-10. RIS Register Definitions; Table 10-9. RIS Register

I
2
S Converter LH79524/LH79525 User’s Guide
10-18 Version 1.0
10.2.2.4 Raw Interrupt Status Register (RIS)
This register provides the current raw status value of the corresponding interrupt prior to
masking. Writing has no effect. For each bit, 1 = TRUE and 0 = FALSE.
The SSPPERIS, ECPERIS and TXUERIS interrupts are set as soon as the given error
conditions are met (a rising edge on the error detection logic). Once cleared by a write to
the appropriate ICR bit, the interrupt bit will not be set again until a new error has been
detected (the next rising edge on the error detection logic). This prevents the interrupt from
being immediately re-set for the same error. The condition causing the error must be
resolved and asserted again to trigger a new interrupt.
Table 10-9. RIS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
SSPPERIS
ECPERIS
TXUERIS
TXRIS
RXRIS
RTRIS
RORRIS
RESET 0000000000001000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC8000 + 0x00C
Table 10-10. RIS Register Definitions
BITS NAME DESCRIPTION
31:7 /// Reserved Reading returns 0. Write the reset value.
6 SSPPERIS
SSP Protocol Error raw interrupt status Indicates that the SSP is
configured for a data size other than 16 bits. Applies only to I
2
S transactions.
Applies to both Slave and Master Mode operation.
5 ECPERIS
External Codec Protocol Error raw interrupt status Indicates that the
external CODEC (the source of the frame input in slave mode) is configured
for a data size other than 16 bits. Applies only to slave mode I
2
S transactions.
4 TXUERIS
Transmit Underrun Error raw interrupt status Transmission has
begun while the transmit FIFO is empty. Applies to SSP and slave mode
I
2
S transactions.
3TXRIS
Transmit FIFO raw interrupt status (from SSP RIS:TXRIS bit) Gives the
raw interrupt state (prior to masking) of the Transmit FIFO interrupt.
2RXRIS
Receive FIFO raw interrupt status (from SSP RIS:RXRIS bit) Gives the
raw interrupt state (prior to masking) of the Receive FIFO interrupt.
1RTRIS
Receive timeout raw interrupt status (from SSP RIS:RTRIS bit) Gives
the raw interrupt state (prior to masking) of the Receive Timeout interrupt
0 RORRIS
Receive overrun raw interrupt status (from SSP RIS:RORRIS bit) Gives
the raw interrupt state (prior to masking) of the Receive Overrun interrupt