Sharp LH79524 - LCD Clock Prescaler Register (LCDPRE); Table 13-34. LCDPRE Register; Table 13-35. LCDPRE Fields; Table 13-36. LCDPRE Register Values

LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller
Version 1.0 13-25
13.2.2.15 LCD Clock Prescaler Register (LCDPRE)
The value in this register is used as a divisor for HCLK to derive the LCD Data Clock
(LCDDCLK) frequency. Following reset, the prescaler is programmed to pass the clock
through without division. Table 13-36 shows the valid combinations for LCDDIV and the
resulting LCDDCLK frequency. All other LCDDIV values are invalid.
Table 13-34. LCDPRE Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// LCDDIV
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
ADDR 0xFFFE2000 + 0x40
Table 13-35. LCDPRE Fields
BITS NAME DESCRIPTION
31:8 /// Reserved Reading returns 0. Write the reset value.
7:0 LCDDIV
LCD Data Clock Divisor Program with the divisor for the LCD Data Clock
prescaler.
Table 13-36. LCDPRE Register Values
LCDDIV
DIVIDER
VALUE
ƒ(LCD)
0b00000000 (default) 1 ƒ(HCLK)
0b00000001 2 ƒ(HCLK)/2
0b00000010 4 ƒ(HCLK)/4
0b00000100 8 ƒ(HCLK)/8
0b00001000 16 ƒ(HCLK)/16
0b00010000 32 ƒ(HCLK)/32
0b00100000 64 ƒ(HCLK)/64
0b01000000 128 ƒ(HCLK))/128
0b10000000 256 ƒ(HCLK)/256