LH79524/LH79525 User’s Guide I
2
S Converter
Version 1.0 10-15
10.2.2.1.1 Implementation of WSDEL
WSDEL is used to delay the assertion of the frame input/output. During master mode, if
WSDEL = 1, then the frame output from the SSP is delayed by one clock before being
asserted on the PB2/SSPFRM/I2SWS pin. If WSDEL = 0, then frame output is passed
through without additional delay. During slave mode, if WDSEL = 0 the frame input is
delayed by one clock before being asserted to the SSP so that the SSPFSSIN pulse coin-
cides with the MSB of the data. If WSDEL = 1, the frame input is passed to the SSP without
additional delay.
10.2.2.1.2 Implementation of WSINV
As seen in Table 10-4, if the WSINV = 0, a logic low on the PB2/SSPFRM/I2SWS pin indi-
cates that the left channel is transmitting, while a logic high indicates that the right channel
is transmitting. If the WSINV bit is set, then a logic low on the PB2/SSPFRM/I2SWS pin
indicates that the right channel is transmitting, while a logic high indicates that the left
channel is transmitting. After reset, the default value of WSINV is a logic low, indicating the
left channel.
Table 10-4. WSINV Functionality
WSINV PB2/SSPFRM/I2SWS = 0 PB2/SSPFRM/I2SWS = 1
0 Left Right
1 Right Left
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