Sharp LH79524 - AHB Clock Control Register (AHBCLKCTRL); Table 13-26. AHBCLKCTRL Register; Table 13-27. AHBCLKCTRL Fields

LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller
Version 1.0 13-21
13.2.2.11 AHB Clock Control Register (AHBCLKCTRL)
This register controls the AHB clocks to several peripherals. Programming a bit to 1 disables
the AHB clock to the corresponding peripheral. Following reset, all AHB clocks are enabled.
For unused peripherals, software should program a 1 to the corresponding bit in this reg-
ister to reduce overall power consumption.
Table 13-26. AHBCLKCTRL Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// LCD USB
ETHERNET
SDRAM
DM
A
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW
ADDR 0xFFFE2000 + 0x2C
Table 13-27. AHBCLKCTRL Fields
BITS NAME DESCRIPTION
31:5 /// Reserved Reading returns 0. Write the reset value.
4LCD
AHB LCD Clock
1 = Disables the LCD AHB clock
0 = Enables the LCD AHB peripheral clock
3USB
AHB USB Clock
1 = Disables the USB AHB clock
0 = Enables the USB AHB peripheral clock
2 ETHERNET
AHB ETHERNET Clock
1 = Disables the ETHERNET AHB clock
0 = Enables the ETHERNET AHB peripheral clock
1 SDRAM
AHB External SDRAM Controller Clock
1 = Disables the SDRAM AHB clock
0 = Enables the SDRAM AHB peripheral clock
0DMA
AHB DMA Clock
1 = Disables the DMA AHB clock
0 = Enables the DMA AHB peripheral clock