Sharp LH79524 - Static Memory Write Delay Registers (Swaitwrx); Table 7-62. Swaitwrx Register; Table 7-63. Swaitwrx Fields

External Memory Controller LH79524/LH79525 User’s Guide
7-58 Version 1.0
7.5.2.26 Static Memory Write Delay Registers (SWAITWRx)
The Static Memory Write Delay Registers enable programming the number of Write wait
states. See Section 7.2.4.1.2 for a complete description of programming these registers.
Wait states behave slightly differently for Write transactions than for Reads. Instead
of the length of the Write cycle (tWC) being the sum of the valued programmed into the
SWAITWENx and SWAITWRx registers, it has the following relationship (with ‘A’ being
SWAITWENx, ‘B’ being SWAITWRx, and ‘C’ being the address hold time):
tWC = tA0 + tB0 + tB1 ... tBn + C, where the length of each term is one HCLK period, and
‘n’ isthe value programmed in the respective register.
The minimum value for the equation is tWC = tA0 + tB0 + C, and is therefore the zero wait
state timing.
Note that additional ‘A’ terms (delaying the assertion of nWE or nBLEx) do not add wait
states. This also requires that: SWAITWRx
≥ SWAITWENx
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
Table 7-62. SWAITWRx Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// WAITWR
RESET 0000000000011111
TYPE RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW
ADDR
0xFFFF1000 + 0x214 for SWAITWR0
0xFFFF1000 + 0x234 for SWAITWR1
0xFFFF1000 + 0x254 for SWAITWR2
0xFFFF1000 + 0x274 for SWAITWR3
Table 7-63. SWAITWRx Fields
BITS NAME FUNCTION
31:5 /// Reserved Reading returns 0. Write the reset value.
4:0 WAITWR
Write Wait States Program with the number of required Write wait
states. See Section 7.2.4.1.2 for timing examples.