Sharp LH79524 - Static Memory Output Enable Delay Registers (Swaitoenx); Table 7-56. Swaitoenx Register; Table 7-57. Swaitoenx Fields

LH79524/LH79525 User’s Guide External Memory Controller
Version 1.0 7-55
7.5.2.23 Static Memory Output Enable Delay Registers (SWAITOENx)
The Static Memory Output Enable Delay Registers enable programming the delay from the
Valid Address to nOE assertion. See Section 7.2.4.1.1 for a complete description of pro-
gramming these registers.
The total Read cycle time is the total time that the address is valid. During this time, several
parameters are programmable. In the following equations, ‘D’ represents the SWAITOENx
register, ‘E’ represents the SWAITRDx register, and ‘C’ represents the address hold time.
In general, Read wait states can be derived from the following equation:
tRC (Read cycle time) = tD1 + tD2 + ... tDn + tE0 + tE1 + ... tEn + C, where the length of
each term is one HCLK period, and ‘n’ is the value programmed in the respective register.
The minimum value for the equation is tRC = tE0 + C, and is therefore the zero wait
state timing.
Thus, Read wait states can be programmed using the appropriate mix of nOE extension
(programmed in SWAITRDx) with nOE assertion delay (programmed in SWAITOENx).
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
Table 7-56. SWAITOENx Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// WAITOEN
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
ADDR
0xFFFF1000 + 0x208 for SWAITOEN0
0xFFFF1000 + 0x228 for SWAITOEN1
0xFFFF1000 + 0x248 for SWAITOEN2
0xFFFF1000 + 0x268 for SWAITOEN3
Table 7-57. SWAITOENx Fields
BITS NAME FUNCTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3:0 WAITOEN
Wait Output Enable Delay from Valid Address to assertion of nOE. See
Section 7.2.4.1.1 for timing examples.