Sharp LH79524 - Control Status Register for EP 0 (CSR0); Table 17-28. CSR0 Register; Table 17-29. CSR0 Fields

LH79524/LH79525 User’s Guide Universal Serial Bus Device
Version 1.0 17-21
17.2.3.3 Control Status Register for EP 0 (CSR0)
CSR0 provides control and status bits for Endpoint 0.
Table 17-28. CSR0 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
CLR_SETUP_END
CLR_OUT
SEND_STALL
SETUP_END
DATA_END
SENT_STALL
IN_PKT_RDY
OUT_PKT_RDY
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RW RW RW RO RW RW RW RO
ADDR
0xFFFF5000 + 0x044
(with the INDEX register set to 0)
Table 17-29. CSR0 Fields
BITS NAME FUNCTION
31:8
/// Reserved Reading returns 0. Write the reset value.
7 CLR_SETUP_END
Clear SETUP_END Bit Software programs a 1 to this bit to clear
SETUP_END (bit 4).
1 = Clear the SETUP_END bit to 0
0 = No effect
6 CLR_OUT
Clear OUT_PKT_RDY Bit Software programs a 1 to this bit to
clear OUT_PKT_RDY (bit 1).
1 = Clear the OUTPACKETRDY bit to 0
0 = No effect
5 SEND_STALL
Send STALL Handshake Software writes a 1 to this bit at the same
time it programs a 0 to OUT_PKT_RDY(bit 0) when it decodes an in-
valid token. The USB Host issues a STALL handshake to the current
control transfer. Software must write a 0 to end the STALL condition.
1 = Issue STALL Handshake
0 = End STALL condition
4 SETUP_END
Setup Ends This is a Read Only bit. Software programs this bit to
1 when a control transfer ends, before DATA_END (bit 3) is set. Soft-
ware programs this bit to 0, by writing a 1 to the CLR_SETUP_END
(bit 7) bit. When the USB Host programs this bit to 1, an interrupt is
generated to the CPU. When such a condition occurs, the USB Host
flushes the FIFO, and invalidates CPU access to the FIFO. When
CPU access to the FIFO is invalidated, this bit is programmed to 0.
1 = Control transfer ended
0 = No control transfer end