UARTs LH79524/LH79525 User’s Guide
16-16 Version 1.0
4FEN
FIFO Enable Buffers This bit not only enables and disables the FIFO buffers,
but also controls the mode. When the FIFO is enabled, it is used to buffer receive
and transmit data. When the FIFO is disabled, the UART is in Character Mode,
using just one line in the FIFO to store a single character.
1 = Enables transmit and receive FIFO buffers (FIFO Mode).
0 = FIFOs are disabled (Character Mode); that is, the FIFOs become
one-byte-deep holding registers.
3STP2
Frame Stop Bits This bit sets the number of Stop bits.
1 = Two Stop bits are transmitted at the end of the frame. The receive logic does
not check for two Stop bits being received.
0 = One Stop bit
2EPS
Even Parity Select Bits [7], [2], and [1] work together to set up the parity. See
Table 16-21.
1 PEN
Parity Enable Bits [7], [2], and [1] work together to set up the parity. See
Table 16-21.
0BRK
SEND BREAK This bit commands the UART to enter a Break condition. This
bit must be asserted for at least one complete frame transmission time in order
to generate a break condition. The transmit FIFO contents remain unaffected
during a break condition. For normal use, this bit must be cleared to 0.
1 = A LOW level is continually output on the UARTTXD output, after completing
transmission of the current character
0 = No Break
Table 16-21. Truth Table for 9BIT, SPS, EPS, and PEN bits
9BIT SPS EPS PEN RESULTANT PARITY BIT (TRANSMITTED OR CHECKED)
0 X X 0 Not transmitted or checked
0001Odd parity
0011Even parity
01011
01110
1XXX
For transmission, ADDRESS TRANSMIT is transmitted as
the parity bit for the frame. If the received parity bit = 1, then the
PARITY-ERROR/ADDRESS RECEIVED error is generated.
Table 16-20. UARTLCR_H Fields (Cont’d)
BIT NAME DESCRIPTION
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