UARTs LH79524/LH79525 User’s Guide
16-24 Version 1.0
16.3.2.12 Masked Interrupt Status Register (UARTMIS)
UARTMIS is the Masked Interrupt Status Register. On a read, this register returns the cur-
rent masked status value of the corresponding interrupt. A write has no effect.
Table 16-30. UARTMIS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
OEMIS
BEMIS
PEARMIS
FEMIS
RTMIS
TXMIS
RXMIS
///
CTS0MIS
///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR
UART 0: 0xFFFC0000 + 0x040
UART 1: 0xFFFC1000 + 0x040
UART 2: 0xFFFC2000 + 0x040
Table 16-31. UARTMIS Fields
BIT NAME DESCRIPTION
31:11 /// Reserved Reading returns 0. Write the reset value.
10 OEMIS
Overrun Error Masked Interrupt Status Specifies the masked interrupt
state of the UARTOEINTR interrupt.
1 = Interrupt pending
0 = No interrupt, or interrupt masked
9 BEMIS
Break Error Masked Interrupt Status Specifies the masked interrupt state
of the UARTBEINTR interrupt.
1 = Interrupt pending
0 = No interrupt, or interrupt masked
8 PEARMIS
Parity Error/Address Received Masked Interrupt Status Specifies the
masked interrupt state of the UARTPEARINTR interrupt.
1 = Interrupt pending
0 = No interrupt, or interrupt masked
7FEMIS
Framing Error Masked Interrupt Status Specifies the masked interrupt
state of the UARTFEINTR interrupt.
1 = Interrupt pending
0 = No interrupt, or interrupt masked
6RTMIS
Receive Timeout Masked Interrupt Status Specifies the masked interrupt
state of the UARTRTINTR interrupt.
1 = Interrupt pending
0 = No interrupt, or interrupt masked
5TXMIS
Transmit Timeout Masked Interrupt Status Specifies the masked inter-
rupt state of the UARTTXINTR interrupt.
1 = Interrupt pending
0 = No interrupt, or interrupt masked
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