Sharp LH79524 - Register Definitions; Table 11-2. MUXCTL1 Register; Table 11-3. MUXCTL1 Fields

I/O Configuration LH79524/LH79525 User’s Guide
11-4 Version 1.0
11.2.2 Register Definitions
11.2.2.1 Multiplexing Control 1 Register (MUXCTL1)
This Register allows software to configure pins PI2/ETHERCOL through PL0/LCDVD14. Bits
marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525.
Table 11-2. MUXCTL1 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// PI2 PI1 PI0 PL1 PL0
RESET 0000000000000000
RW RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0x00
Table 11-3. MUXCTL1 Fields
BIT NAME DESCRIPTION
31:10 /// Reserved Reading returns 0. Write the reset value.
9:8 PI2
PI2/ETHERCOL Assignment
00 = PI2
01 = ETHERCOL
10 = Reserved
11 = Reserved
7:6 PI1
PI1/ETHERMDIO Assignment
00 = PI1
01 = ETHERMDIO
10 = Reserved
11 = Reserved
5:4 PI0
PI0/ETHERMDC Assignment
00 = PI0
01 = ETHERMDC
10 = Reserved
11 = Reserved
3:2 PL1
PL1/LCDVD15 Assignment (LH79524 Only)
00 = PL1
01 = LCDVD15
10 = Reserved
11 = Reserved
1:0 PL0
PL0/LCDVD14 Assignment (LH79524 Only)
00 = PL0
01 = LCDVD14
10 = Reserved
11 = Reserved