LH79524/LH79525 User’s Guide UARTs
Version 1.0 16-27
16.3.2.14 UART0 DMA Control Register (DMACTRL)
UART0 DMACTRL is the UART0 DMA Control Register. It allows control of certain UART
DMA functions.
The RXDMAEN, and TXDMAEN bits are not automatically cleared for standard Stream 0
through 3 DMA operations, respectively. These bits should be explicitly cleared by soft-
ware as soon as possible following DMA completion.
On initiating a DMA operation the DMAC:CTRL:ENABLE bit should be set before either of
the above mentioned bits are set.
Table 16-34. DMACTRL Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
DMAOE
TXDMAEN
RXDMAEN
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW
ADDR UART 0: 0xFFFC0000 + 0x048
Table 16-35. DMACTRL Fields
BIT NAME DESCRIPTION
15:3
/// Reserved Reading returns 0. Write the reset value.
2DMAOE
DMA on Error
1 = Disables the DMA receive request output when the UART Error Interrupt is
asserted
0 = Does not disables the DMA receive request output when the UART Error
Interrupt is asserted
1 TXDMAEN
Transmit DMA Enable
1 = Enables the DMA for the transmit FIFO
0 = Disables the DMA for the transmit FIFO
0 RXDMAEN
Receive DMA Enable
1 = Enables the DMA for the receive FIFO
0 = Disables the DMA for the receive FIFO
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