LH79524/LH79525 User’s Guide Vectored Interrupt Controller
Version 1.0 18-7
18.2.2.2 FIQ Status Register (FIQSTATUS)
This Read Only register provides the status of the interrupts after FIQ masking. Bits [31:0]
correspond to the interrupt number in Table 18-1.
18.2.2.3 Raw Interrupt Status Register (RAWINTR)
This Read Only register provides the status of the source interrupts (and software
interrupts) to the VIC. Bits [31:0] correspond to the interrupt number in Table 18-1.
Table 18-5. FIQSTATUS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD FIQStatus
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD FIQStatus
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFFF000 + 0x004
Table 18-6. FIQSTATUS Fields
BITS NAME DESCRIPTION
31:0 FIQStatus
Interrupt Status After Masking Shows the status of the interrupts after
masking by the IntEnable and IntSelect Registers.
For each bit:
1 = Interrupt is active and generates an FIQ exception to the ARM7 core
0 = Interrupt is not active
Table 18-7. RAWINTR Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD RawInterrupt
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD RawInterrupt
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFFF000 + 0x008
Table 18-8. RAWINTR Fields
BITS NAME DESCRIPTION
31:0 RawInterrupt
Raw Interrupt Status Shows the status of the interrupts
before masking by the Interrupt Enable Registers.
For each bit:
1 = Appropriate interrupt request is active before masking
0 = Appropriate interrupt request is not active before masking
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